1. Field of the Invention
This invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, this invention relates to techniques used for system LSIs using SON (Silicon on Nothing) substrates.
2. Description of the Related Art
It is well known that an SOI (Silicon on Insulator) has a structure where a silicon layer is formed on an insulating film. Forming semiconductor elements on such an SOI enables semiconductor integrated circuits to consume less electric power and operate at higher speeds. Methods of forming SOIs include a method of laminating two substrates together and an SIMOX (Separation by Implanted Oxygen) method. SOIs, however, have the disadvantages that they are higher in manufacturing cost and that it is difficult to form a silicon layer with defect-free.
With this backdrop, an SON structure where a silicon layer is provided at the top of a cavity has lately attracted attention. It is safe to say that the SON is the final SOI structure. The SON has the same merits as those of the SOI. The SON is currently under intensive investigation. For example, a method of insulating a silicon layer from a semiconductor substrate has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 5-206257. An SON manufacturing method capable of micro-fabrication has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 8-288381. A method of manufacturing double-gate MOS transistors using SONs has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-257358. An infrared sensor using SON has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-281051. From these, it can be seen that the study of SON has covered various fields.
The configuration of a conventional semiconductor device using an SON structure will be explained by reference to FIG. 1 (for further details, refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-144276). FIG. 1 is a sectional view of a MOS transistor formed on an SON substrate.
As shown in FIG. 1, cavities 110 are made in a semiconductor substrate 100. Then, source and drain regions 120, 120 are formed in an element region AA10 located at the top of the cavity 110. A gate electrode 140 is formed on the element region AA10 with a gate insulating film 130 interposed therebetween, thereby forming a MOS transistor. A sidewall insulating film 170 is formed on the sidewall of the gate electrode 140. Adjacent MOS transistors are electrically separated from one another by an element isolating region 150 formed between them. The element isolating region 150 is formed normally using STI (Shallow Trench Isolation) techniques from the viewpoint of the micro-fabrication of elements.
As described above, the use of SON has been encouraging an attempt to cause semiconductor integrated circuits to consume less power and operate at higher speeds. It is expected that SON will be applied to system LSIs embedded, for example, DRAM (Dynamic Random Access Memory) in the future.
The conventional SON structure, however, tends to make the micro-fabrication of semiconductor devices difficult.
Specifically, as shown in FIG. 1, when SON and STI techniques are used, the element isolating region 150 has to be prevented from exposing to the cavity 110. The reason is that, in the STI technique, trenches are formed in a semiconductor substrate and then, the trenches are filled with an insulating film, thereby forming an element isolating region. If the trenches are exposed to the cavities 110, what supports the element region AA10 will be lost. To avoid this problem, a distance of, for example, d1 is allowed between the cavity 110 and the element isolating region 150. Depending on the situation, the clearance makes a totally useless region, which contributes to an increase in the element area.
Furthermore, in the conventional structure, the region between the cavities 110 and the element isolating region 150 electrically connects the element regions AA10 with the semiconductor substrate 100. To solve this problem, well regions 160, which are unnecessary in the SOI structure, must be used to electrically separate the element region AA10 from the semiconductor substrate 100. As a result, it is difficult to narrow the distance between adjacent semiconductor elements, which may interfere with the micro-fabrication of semiconductor devices.